3d stackable synapse string, 3d stackable synapse array using the string and method of fabricating the string

ABSTRACT

Provided is a 3D stackable synapse string, a 3D stackable synapse array using the same, and a method for manufacturing the 3D stackable synapse string. The 3D stackable synapse stringack comprises: a semiconductor body provided on an outer circumferential surface of a channel hole provided in a form of a pillar shape in a vertical direction; a plurality of first insulating layers located on an outer circumferential surface of the semiconductor body; a plurality of word lines positioned on a first side surface of an outer circumferential surface of the semiconductor body and alternately stacked with first insulating layers on the side surface; an insulator stack positioned between the word lines and the semiconductor body; an device isolation unit located on an outer circumferential surface of the semiconductor body located on both sides of the first side surface, and including second insulating layers alternately stacked with the first insulating layers; and first and second electrodes respectively positioned above and below the channel hole; wherein the word line, the insulator stack, and the semiconductor body located on the first side of the semiconductor body constitute a synapse device or a part thereof, and the synapse devices stacked along the channel hole constitute a synapse string connected by the semiconductor body.

TECHNICAL FIELD

The present invention relates to a three-dimensional stackable synapse string, a three-dimensional stackable synapse array using the same, and a method for manufacturing the three-dimensional stackable synapse string, and more specifically, to a three-dimensional stackable synapse array capable of improving the degree of integration and improving operational reliability by implementing a NAND-type synapse array in a three-dimensional stackable form and a method for manufacturing the same.

BACKGROUND ART

In recent years, many approaches have been made to imitate nervous systems of animals as power consumption has increased significantly and heat release problems have become more serious in integrated circuits based on the von Neumann architecture. Particularly, in the techniques imitating the nervous systems of animals, it is possible to improve the cognitive function and the determining function by enabling cognitive function and learning while greatly reducing power consumption. As a result, there is an opportunity to replace or greatly improve the functionality of the existing von Neumann integrated circuits. Therefore, much attention has been increasingly paid to the techniques, and the need for research has been greatly increased.

The basic function of neurons is to generate electrical spikes and transmit information to other cells in a case where a stimulus exceeds a threshold value. The resulting electrical signal is called an action potential. Neurons may be roughly divided into three portions. The neuron includes a nerve cell body where a nucleus exists, a dendrite which receives a signal from another cell, and an axon which transmits a signal to another cell. A portion which transmits a signal between the dendrites is called a synapse.

The neuron receives a stimulus from another nerve cell or a stimulus receptor cell and transmits the stimulus to another nerve cell or a glandular cell. Exchanging the stimulus occurs at the synapse. One nerve cell (neuron) receives stimuli through a number of synapses and integrates the excitations, and after that, the nerve cell transmits an electrical spike to an axon near to the nerve cell body, so that the electrical spike reaches the synapse. In this manner, the transmission of the excitations from the neuron through the synapses to another nerve cell is referred to as excitation transmission. The excitation at the synapse is transmitted only from a nerve fiber toward a nerve cell body or a dendrite and is not transmitted in the reverse direction, so that the excitation is transmitted in only one direction as a whole. In addition, the synapses are not only relay sites that transmit the excitations but the synapses also cause weighting or inhibition according to temporal or spatial change in excitations reaching the synapses to enable higher level integration of the nervous system.

On the other hand, besides the synapses having the action of transmitting the excitation, there are synapses having the action of inhibiting the transmission of the excitations from other nerve cells. These synapses are called inhibitory synapses. When the excitation transmitted along some nerve fibers reaches the inhibitory synapse, the inhibitory transmitting material is secreted from the synapse. This inhibitory transmitting material acts on a cell membrane of the nerve cell connected to the synapse to inhibit the excitations of the cell from occurring (occurrence of an action potential). As a result, while the inhibitory transmitting material acts, the excitation reaching other synapses is not transmitted to the synapse.

Recently, various studies have been conducted to implement neural networks using RRAM devices (Xiaoyu Sun et al., “XNOR-RRAM: A Scalable and Parallel Resistive Synapse Architecture for Binary Neural Networks”, 2018 Design, Automation & Test in Europe Conference & Exhibition). However, in the case of Memristor-based synapses of the prior art, there is a disadvantage in that the reliability of the device is not good and the dispersion between the devices is large.

Also, recent attempts have been made to implement neural networks using SRAM devices (Si, X., et al., “A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning” In 2019 IEEE International Solid-State Circuits Conference-(ISSCC), pp. 396-398) However, implementing a neural network using an SRAM device according to the above-described prior art has good reliability, but has a disadvantage of low integration by using multiple devices.

Therefore, the present invention provides three-dimensional stackable synapse array architectures that can operate with low power and high reliability while increasing the degree of integration.

SUMMARY OF THE INVENTION

191 In order to solve the problems of the prior art described above, an object of the present invention is to provide a three-dimensional stackable synapse string that can be implemented as a NAND-type synapse array, and has an excellent degree of integration and improved reliability.

Another object of the present invention is to a three-dimensional stackable synapse array using the three-dimensional stackable synapse string.

Another object of the present invention is to provide a method for manufacturing the three-dimensional stackable synapse string.

According to one aspect of the present invention, there is provided a three-dimensional stackable synapse string, which comprises: a channel hole formed in a pillar shape provided in a vertical direction, the inside of which is filled with an insulating material; a semiconductor body located on the surface of the channel hole and provided on the surface of the channel hole in the form of a thin layer; a plurality of first insulating layers disposed on an outer circumferential surface of the semiconductor body and spaced apart from each other and stacked; a plurality of word lines disposed on a first side surface of an outer circumferential surface of the semiconductor body and alternately provided with first insulating layers disposed on the first side surface; a plurality of insulator stacks positioned between the word lines and the semiconductor body; an device isolation unit positioned on an outer circumferential surface of the semiconductor body located on both sides of the first side surface, and including second insulating layers alternately stacked with the first insulating layers; a first electrode disposed on the channel hole and electrically connected to a first end of the semiconductor body; and a second electrode disposed under the channel hole and electrically connected to a second end of the semiconductor body;

wherein the word line, the insulator stack, and the semiconductor body located on the first side of the semiconductor body constitute a synapse device or a part thereof, and the synapse devices stacked along the vertical direction of the channel hole constitute a synapse string connected by the semiconductor body.

In the three-dimensional stackable synapse string according to the present invention, preferably the three-dimensional stackable synapse string is provided on a substrate having an upper surface formed of a first oxide layer, and the second electrode is provided in the surface of the first oxide layer.

In the three-dimensional stackable synapse string according to the present invention, preferably the three-dimensional stackable synapse string according to claim 1, wherein among the surface of the channel hole, the region where the synapse device is formed is protruded toward the word line and extended.

In the three-dimensional stackable synapse string according to the present invention, preferably the insulator stack is composed of a single insulating layer or a stack structure in which a plurality of layers are stacked; and when configured in a stack structure, the insulator stack comprises at least a charge storage layer and an insulating layer, at least a ferroelectric layer and an insulating layer, at least a resistance change layer and an insulating layer, or at least a phase change layer and an insulating layer.

In the three-dimensional stackable synapse string according to the present invention, preferably the synapse string further comprises: a first electrode landing pad positioned on the first electrode, made of an electrically conductive material, and electrically connected to the first electrode; and a second electrode landing pad positioned in the first oxide layer located under the second electrode, made of an electrically conductive material, and electrically connected to the second electrode.

In the three-dimensional stackable synapse string according to the present invention, preferably the synapse string further comprises an additional synapse string which includes: a plurality of additional word lines disposed on a second side surface of an outer circumferential surface of the semiconductor body opposite to the first side surface and alternately stacked with first insulating layers disposed on the second side surface; and a plurality of additional insulator stacks positioned between the additional second word lines and the semiconductor body; wherein the additional word line, the additional insulator stack and the semiconductor body located on the second side of the semiconductor body constitute an additional synapse device or a part thereof, and the additional synapse devices stacked along the vertical direction of the channel hole constitute an additional synapse string connected by a semiconductor body, respectively.

In the three-dimensional stackable synapse string according to the present invention, preferably the synapse string and the additional synapse string may share the first electrode and the second electrode, or may share a first electrode and include a second electrode separately.

According to another aspect of the present invention, there is provided a three-dimensional stackable synapse array, characterized in that the three-dimensional synapse device strings according to the present invention are arranged in an array form.

In the three-dimensional stackable synapse array according to the present invention, preferably the synapse array further comprises a CMOS integrated circuit used as a peripheral circuit under the substrate.

According to another aspect of the present invention, there is provided a method of manufacturing a three-dimensional stackable synapse string comprising the following steps: (a) forming a first oxide layer on a substrate, forming a second electrode landing pad on the first oxide layer, and planarizing the surface of the resultant; (b) alternately forming first insulating layers and second insulating layers on the surface of the first oxide layer on which the second electrode landing pad is formed to form a stacked structure; (c) etching predetermined regions of the stacked structure by using a photolithography process to simultaneously form an etch hole and a trench for string isolation, forming a passivation material in the etched regions of the stacked structure, and planarizing the surface; (d) etching the passivation material filled in the etch hole, depositing a semiconductor material to be used as a channel on the surface of the etch hole to form a semiconductor body, filling the inside of the etch hole in which the semiconductor body is formed with an oxide material, and planarizing it; (e) forming a first electrode landing pad on an upper portion of the semiconductor body; and (f) selectively etching the passivation material filled in the trench for string isolation, selectively etching second insulating layers from the surface of the trench for string isolation to be recessed, forming insulator stacks on the surfaces of the recessed spaces; and forming a plurality of word lines separated by layers by depositing and etching a conductive material;

In the method of manufacturing a three-dimensional stackable synapse string according to present invention, preferably in the step (d), the passivation material filled in the etching hole is selectively etched, and the second insulating layers of the stacked structure are selectively etched and recessed to form a channel hole; and the semiconductor body made of a semiconductor material to be used as a channel is formed on the surface of the channel hole, and the inside of the channel hole in which the semiconductor body is formed is filled with an oxide material and then planarized the surface.

In the method of manufacturing a three-dimensional stackable synapse string according to present invention, preferably the first insulating layer and the second insulating layer are made of materials having different etch ratios.

The 3D stackable synapse string according to the present invention having the above-described structure and the 3D stackable synapse array using the same implement the synapse devices in a three-dimensional stacked type, thereby significantly improving the degree of integration.

In addition, according to the present invention, by adjusting the voltages applied to each electrode, selective program and selective erase operations are possible for each layer and each position with respect to the synapse strings constituting the 3D stackable synapse array. As a result, the 3D stackable synapse array according to the present invention not only improves performance, but also improves reliability.

The 3D stackable synapse array according to the present invention having the above-described structure can be implemented as a capacitor using the insulator stack of each synapse device, and as a result, a capacitor stack structure can be provided by using the structure of the 3D stackable synapse string as it is.

In addition, the 3D stackable synapse array according to the present invention having the above-described structure provides a source electrode and a drain electrode landing pads on a substrate, so that a CMOS circuit can be easily integrated and connected to the lower portion of the 3D stackable synapse string.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view showing a three-dimensional stackable synapse string according to a preferred embodiment of the present invention,

FIG. 2 is a cross-sectional view taken along the A-A direction of FIG. 1 , FIG. 3A is a cross-sectional view taken in the first direction of FIG. 2 , and

FIG. 3B is a cross-sectional view taken in the second direction of FIG. 2 .

FIG. 4 is a flowchart sequentially illustrating a method for manufacturing a three-dimensional stackable synapse string according to a preferred embodiment of the present invention shown in FIG. 3 , and

FIGS. 5A and 5B are cross-sectional views and Top Views showing the results of each step of FIG. 4 .

FIGS. 6A and 6B are cross-sectional views in first and second directions illustrating another embodiment of a channel hole in a three-dimensional stackable synapse string according to a preferred embodiment of the present invention.

FIG. 7 is cross-sectional views and Top Views showing the results of some steps in the manufacturing method of the three-dimensional stackable synapse string of the present invention shown in FIG. 6 .

FIG. 8 is a perspective view showing another embodiment of a second electrode in a three-dimensional stackable synapse string according to a preferred embodiment of the present invention,

FIG. 9 is a cross-sectional view taken along the A-A direction of FIG. 8 ,

FIG. 10A is a cross-sectional view taken in the first direction of FIG. 9 , and FIG. 10B is a cross-sectional view taken in the second direction of FIG. 9 .

FIG. 11 is cross-sectional views and Top Views showing the results of some steps in the manufacturing method of the three-dimensional stackable synapse string of the present invention shown in FIG. 8 .

FIGS. 12 and 13 are a cross-sectional view and an equivalent circuit diagram illustrating an example of a NAND-type synapse array structure configured using three-dimensional stackable synapse arrays using a three-dimensional stackable synapse string according to the present invention.

FIG. 14 is a schematic diagram illustrating the degree of integration in the three-dimensional stackable synapse string according to the present invention.

FIGS. 15A and 15B are an equivalent circuit diagram and a table showing voltages applied to each terminal for explaining a selective program operation for a target device in a three-dimensional stackable synapse array according to the present invention.

FIGS. 16A and 16B are graphs of read results for a synapse device (CELL A) that has performed a selective program operation and a synapse device (CELL B) that does not perform a selective program operation according to the selective program operation according to FIGS. 15A and 15B.

FIGS. 17A and 17B are an equivalent circuit diagram and a table showing voltages applied to each terminal for explaining a selective erase operation for a target device in the three-dimensional stackable synapse array structure shown in FIG. 16 .

FIGS. 18A and 18B are graphs of read results for a synapse device (CELL A) that has performed a selective program operation and a synapse device (CELL B) that does not perform a selective program operation according to the selective program operation according to FIG. 17 .

DETAILED DESCRIPTION

Hereinafter, a three-dimensional stackable synapse string made of synapse devices according to the present invention, a three-dimensional stackable synapse array using the three-dimensional stackable synapse string, and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

<3D Stackable Synapse String>

FIG. 1 is a perspective view showing a three-dimensional stackable synapse string according to a preferred embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the A-A direction of FIG. 1 , FIG. 3A is a cross-sectional view taken in the first direction of FIG. 2 , and FIG. 3B is a cross-sectional view taken in the second direction of FIG. 2 .

Hereinafter, with reference to FIGS. 1 to 3 , the structure and operation of a three-dimensional stackable synapse string according to a preferred embodiment of the present invention will be described in detail. For convenience, in the present specification, a three-dimensional stackable synapse string is described assuming that the cell devices have a stacked structure of three layers. However, the three-dimensional stackable synapse string according to the present invention is not limited to the three-layer stacked structure of the cell devices, and may be manufactured as a stacked structure consisting of a plurality of more layers if necessary.

Referring to FIGS. 1 to 3 , the three-dimensional stackable synapse string 1 according to a preferred embodiment of the present invention includes a substrate (not shown), a channel hole 110, a semiconductor body (Body) 120, a plurality of first insulating layers (Oxide2) 130, a first electrode (DL) 140, a second electrode (SL) 150, a plurality of word lines (WL) 160, and a plurality of insulator stacks 170. In the three-dimensional stackable synapse string having the above configuration, the semiconductor body, the insulator stack, and the word line positioned on the same layer on the first side of the channel hole constitute the synapse device or a part thereof. And, the synapse devices are isolated from each other by the first insulating layers, and electrically connected in series by the semiconductor body. And, the first and second electrodes are provided at both ends of the series-connected synapse devices, respectively. Accordingly, the synapse devices and the first insulating layers are alternately arranged on the first side of the channel hole to form a stackable synapse string.

Hereinafter, each of the above-described components will be described in detail.

The upper surface of the substrate is made of a first oxide layer (Oxide 1) 100, and the three-dimensional stackable synapse string according to the present invention is provided along a vertical direction on the first oxide layer 100 of the substrate.

The channel hole 110 is located above the first oxide layer 100 on the upper surface of the substrate, and is a hole provided in a pillar shape along a direction perpendicular to the surface of the substrate, and the inside of the channel hole is filled with an oxide material (Oxide 3) having electrical insulation properties.

The semiconductor body 120 is positioned on the surface of the channel hole, and is provided by applying a semiconductor material to the surface of the channel hole in the form of a thin layer. The semiconductor body may be made of a semiconductor material such as polysilicon, poly-SiGe, metal oxide, or the like. The semiconductor body 120 having the above-described structure is configured to form a channel during device operation.

The plurality of first insulating layers (Oxide 2) 130 are positioned on the outer circumferential surface of the semiconductor body, are spaced apart from each other along the outer circumferential surface of the semiconductor body, and are vertically stacked. The first insulating layer may be formed of, for example, an oxide layer (Oxide 2). The first insulating layers electrically insulate the stackable synapse devices from each other.

The plurality of word lines 160 are positioned on a first side surface of an outer circumferential surface of the semiconductor body, and are alternately stacked with first insulating layers. The plurality of insulator stacks 170 are provided between at least the word lines and the semiconductor body, and may be further provided between the word lines and the first insulating layers. The insulator stack may be composed of a single layer or a stack structure in which at least two or more layers are stacked, and the insulator stack includes a layer that stores electric charges or causes polarization.

When the insulator stack is composed of a single layer, it may be formed of an oxide layer, a nitride layer, or the like. And, when the insulator stack is configured in a stack structure, it may include at least a charge storage layer and an insulating layer, a ferroelectric layer and an insulating layer, a resistance change layer and an insulating layer, or a phase change layer and an insulating layer.

The insulator stack preferably has a stack structure in which a plurality of layers including at least a charge storage layer and an insulating layer are stacked, and the structure of the insulator stack may be implemented in various embodiments. On the other hand, when the insulator stack includes a charge storage layer and an insulating layer, preferably no insulating layer or an insulating layer with a thickness of 4 nm or less is disposed between the semiconductor body and the charge storage layer, so that the operating voltage can be lowered.

In addition, the insulator stack may be configured by stacking a plurality of insulating layers. In this case, at least one of the insulating layers constituting the insulator stack includes an insulating layer having a trap for enabling charge storage, and the insulating layer operates as a charge storage layer, so that the device can implement a memory function for storing information in a non-volatile form. For example, the insulator stack may be formed in a stacked structure of a first insulating layer, a charge storage layer, and a second insulating layer, or may be formed in a stacked structure of an insulating layer and a charge storage layer. Here, the insulating layer of the insulator stack may use silicon oxide, aluminum oxide, etc., and the charge storage layer may use silicon nitride, hafnium oxide, or the like.

In addition, at least one of the insulating layers constituting the insulator stack may implement a memory function for storing information in a non-volatile form using a polarization-inducing material. For example, the insulator stack may be formed in a stacked structure of a material layer causing polarization and an insulating layer. Here, the insulating layer of the insulator stack may be formed of silicon oxide, aluminum oxide, or the like, and a plurality of materials including hafnium oxide (HfZrOx) may be used as the polarization-inducing material.

The three-dimensional stackable synapse string according to the present invention preferably further includes device isolation units located on the outer peripheral surface of the semiconductor body located on both sides of the first side surface provided with cell devices. The device isolation part includes second insulating layers 132 alternately stacked with first insulating layers, and the second insulating layers 132 may be, for example, a nitride layer.

FIGS. 2 and 3 , a plurality of word lines and first insulating layers are alternately stacked on the side surface of the channel hole in the first direction. In addition, a plurality of first insulating layers and second insulating layers are alternately stacked on opposite side surfaces of the channel hole in the second direction.

The first electrode (DL) 140 is disposed on the channel hole and is electrically connected to a first end of the semiconductor body. The second electrode (SL) 150 is disposed under the channel hole and is electrically connected to a second end of the semiconductor body. The first and second electrodes are made of a material having electrical conductivity, and for example, may be made of one of various metals, silicides, or semiconductor materials doped with impurities. The semiconductor material may include an amorphous semiconductor, a single crystal semiconductor, a polycrystalline semiconductor, and the like.

On the other hand, the three-dimensional stackable synapse string according to the present invention further includes an additional stackable synapse string having the same structure on the second side of the channel hole opposite to the first side, thereby further improving the degree of integration. The additional stackable synapse string includes additional word lines and additional insulator stacks, and is configured to share a first electrode and a second electrode of the stackable synapse string. Here, the additional synapse device has the same structure as the aforementioned synapse device, the additional word line has the same structure as the aforementioned word line, and the additional insulator stack has the same structure as the aforementioned insulator stack.

Accordingly, two stackable synapse strings sharing the first electrode and the second electrode are provided on the first and second sides of the channel hole. The present invention can provide a basic synapse device or a part thereof that can be effectively implemented in a three-dimensional string structure, and can improve the degree of integration and the performance of the device by the above-described structure. And, the three-dimensional stackable synapse string having the above-described structure can be applied to various array architectures, and preferably can be applied to NAND device-type Synapse Array Architecture.

Hereinafter, with reference to FIGS. 4 and 5 , a method for manufacturing the above-described three-dimensional stackable synapse string will be described in detail.

FIG. 4 is a flowchart sequentially illustrating a method for manufacturing a three-dimensional stackable synapse string according to a preferred embodiment of the present invention shown in FIG. 3 , and FIGS. 5A and 5B are cross-sectional views and Top Views showing the results of each step of FIG. 4 .

Referring to FIGS. 4 and 5A and 5B, first, a first oxide layer is formed on a substrate, a thin layer made of a semiconductor material doped with N+ is formed thereon in a first direction, and then patterned through a photolithography process to form a second electrode (step 100, (a) of FIG. 5A). Here, polysilicon may be used as the semiconductor material. Then, an oxide layer is formed on the resultant having the second electrode and then planarized the surface ((b) of FIG. 5A).

Next, a stacked structure is formed by alternately and repeatedly forming first insulating layers and second insulating layers on the planarized surface (step 102, (c) of FIG. 5A).

Preferably, the first insulating layer and the second insulating layer are made of materials having different etch ratios, so that while the first insulating layers are etched, the second insulating layers are hardly etched, and while the second insulating layers are etched, the first insulating layers are hardly etched. Here, an oxide layer may be used as the first insulating layer, and a nitride layer may be used as the second insulating layer. Then, predetermined regions of the stacked structure are etched using a photolithography process to simultaneously form an etch hole and a trench isolation for strings (step 110, (d) of FIG. 5A). Then, after depositing a passivation material on the etched regions of the stack structure, the surface is planarized (step 120, (e) of FIG. 5A). The passivation material may be polysilicon. Then, a channel hole is formed by selectively etching the passivation material filled in the etching hole to expose the etching hole (step 130, (f) of FIG. 5A).

Next, a semiconductor body made of a semiconductor material to be used as a channel is formed on the surface of the channel hole (step 140, (g) of FIG. 5A). The inside of the channel hole in which the semiconductor body is formed is filled with an oxide material and planarized the surface (step 150, (h) of FIG. 5A). Then, a first electrode is formed on the semiconductor body (step 160, (i) of FIG. 5B).

Next, a passivation material of the trench for string isolation is selectively etched to expose the trench for string isolation (step 170, (j) of FIG. 5B). Then, after selectively etching the second insulating layers from the exposed surface of the trench for string isolation (step 180, (k) of FIG. 5B), insulator stacks are formed on the surfaces of the recessed spaces, and a conductive material are formed and isotropically etched to form a plurality of word lines separated by layers (step 190, (1) of FIG. 5B).

Next, the inside of the trench for string isolation is filled with an oxide material and then planarized the surface (step 210, (m) of FIG. 5B). Through the above-described manufacturing process, a three-dimensional stackable synapse string according to a preferred embodiment of the present invention is completed.

FIGS. 6A and 6B are cross-sectional views in first and second directions illustrating another embodiment of a channel hole in a three-dimensional stackable synapse string according to a preferred embodiment of the present invention.

Referring to FIGS. 6A and 6B, the regions in which the synapse devices are formed among the surface of the channel hole protrude toward the word lines and extend. And, as the semiconductor body is provided on the surface of the channel hole, the semiconductor body is formed as a thin layer in a zigzag shape in a vertical direction.

FIG. 7 is cross-sectional views and Top Views showing the results of some steps in the manufacturing method of the three-dimensional stackable synapse string of the present invention shown in FIGS. 6A and 6B.

Referring to FIG. 7 , the manufacturing method of the three-dimensional stackable synapse string according to the present embodiment is basically the same as the process described in FIGS. 4 and 5A and 5B, except that after the step of forming the channel hole (step 130) by selectively etching the passivation material filled in the etch hole, the following processes are further provided. The second insulating layers are partially etched from the surface of the channel hole to be partially recessed (step 132, (a) of FIG. 7 ), and the first insulating layers are etched from the surface of the channel hole to expose the surface of the second electrode (step 134, (b) of FIG. 7 ), and a semiconductor body made of polysilicon to be used as a channel is formed on the surface of the channel hole (step 136, (c) of FIG. 7 ). In this way, by further comprising the steps 132 to 136 described above, the surface of the channel hole where the synapse devices are to be formed is protruded.

Hereinafter, with reference to the accompanying drawings, in a three-dimensional stackable synapse string according to a preferred embodiment of the present invention, another embodiment of the second electrode will be described.

FIG. 8 is a perspective view showing another embodiment of a second electrode in a three-dimensional stackable synapse string according to a preferred embodiment of the present invention, FIG. 9 is a cross-sectional view taken along the A-A direction of FIG. 8 , FIG. 10A is a cross-sectional view taken in the first direction of FIG. 9 , and FIG. 10B is a cross-sectional view taken in the second direction of FIG. 9 .

Referring to FIGS. 8 to 10 , the first synapse string and the second synapse string provided on both sides of one channel hole include second electrodes 150 and 152 separated from each other, respectively.

FIG. 11 is cross-sectional views and Top Views showing the results of some steps in the manufacturing method of the three-dimensional stackable synapse string of the present invention shown in FIG. 8 .

Referring to FIG. 11 , the manufacturing method of the three-dimensional stackable synapse string according to the present embodiment is basically the same as the process described in FIGS. 4 and 5 , and in the step of forming the second electrode on the substrate, the second electrodes separated from each other in one channel hole are patterned and provided.

<3D Stackable Synapse Array>

The three-dimensional stackable synapse array according to the present invention may be configured by sequentially arranging the three-dimensional stackable synapse string having the above-described structure. In addition, a NAND-type synapse array can be configured by arranging three-dimensional stackable synapse strings.

FIGS. 12 and 13 are a cross-sectional view and an equivalent circuit diagram illustrating an example of a NAND-type synapse array structure configured using three-dimensional stackable synapse arrays using a three-dimensional stackable synapse string according to the present invention.

Referring to FIGS. 12 and 13 , in the NAND-type synapse array according to the present invention, the first electrodes (DL1, DL2, DL3) and the second electrodes (SL1, SL2, SL3, SL4) connected to each synapse string are disposed in a direction perpendicular to each other, and the stacked string structures are repeatedly arranged so that word lines are arranged.

FIG. 14 is a schematic diagram illustrating the degree of integration in the three-dimensional stackable synapse string according to the present invention.

When the size of one cell in the structure according to the present invention is calculated with reference to FIG. 14 , since two strings occupy the stack width (4F)+isolation (1F) in the first direction and the spacing between cells (2F) in the second direction, the area effectively occupied by one string becomes 5F².

<Selective Program and Erase Operations>

Hereinafter, in the three-dimensional stackable synapse array according to the present invention, selective program and selective erase operations for a target device will be described with reference to the accompanying drawings.

FIGS. 15A and 15B are an equivalent circuit diagram and a table showing voltages applied to each terminal for explaining a selective program operation for a target device in a three-dimensional stackable synapse array according to the present invention.

The three-dimensional stackable synapse array shown in FIG. 15 is a three-dimensional stackable synapse array structure in which three layers are vertically stacked and two pairs of devices are horizontally provided, and it consists of 6 WLs and two SLs and DLs, and is a NAND type synapse array.

Referring to FIGS. 15A and 15B, first, a preset program voltage V_(PGM) is applied to the WL of a layer to be programmed, and 0 V is applied to the first electrode (DL) and the second electrode (SL) connected to the WL, respectively, so that electrons are injected using the F-N tunneling mechanism. At this time, a preset first pass voltage (Vpass 1) is applied to WL1-3 of the layer between the target device and the first electrode, 0 V is applied to WLs of another adjacent layers, and a preset second pass voltage (Vpass 2) is applied to another adjacent DLs to block the program operation. Here, V_(PGM) is a positive voltage large enough to cause F-N tunneling in the first insulator stack that separates the WL line and the body region. In addition, Vpass 1 is a positive voltage enough to form a channel by turning on all devices of other adjacent layers of the same string. Vpass 2 is a positive voltage enough to reduce the voltage difference with V_(PGM) so that F-N tunneling does not occur in neighboring cells sharing WL with the target cell. It is generally desirable to have half the V_(PGM) value. A voltage of Vpass 1 is applied to WLs of other layers adjacent to the target cell to transmit the voltage of the first electrode to all channels.

FIGS. 16A and 16B are graphs of read results for a synapse device (CELL A) that has performed a program operation and a synapse device (CELL B) that does not perform a program operation according to the selective write operation according to FIGS. 15A and 15B.

FIGS. 16A and 16B are a result of measuring the current flowing in DL1 by applying a turn-on voltage to WL of the target cell after electrons are injected into the target cell under the above-described conditions of FIGS. 15A and 15B.

FIG. 16A is a graph of a read result for CELL A, which is a device on which a selective program operation has been performed. The left line is the current in the initial state, and the right line is the current after the selective program operation. Referring to FIG. 16A, it can be seen that the current flowing through CELL A is decreased from the initial state and changed after the selective program operation. Meanwhile, FIG. 16B is a graph of a read result for CELL B, which is a device on which a program operation is not performed. Referring to FIG. 16B, it can be confirmed that the current flowing through CELL B after the selective program operation on CELL A is the same as the initial state. That is, since FN tunneling does not occur in CELL A's neighbor CELL B, the graph hardly changes.

FIGS. 17A and 17B are an equivalent circuit diagram and a table showing voltages applied to each terminal for explaining a selective erase operation for a target device in the three-dimensional stackable synapse array structure shown in FIGS. 16A and 16B.

Referring to FIGS. 17A and 17B, in the structure according to the present invention, holes are generated using a hot-hole injection (HHI) mechanism. In the structure according to the present invention, the erase operation occurs simultaneously in the synapse devices sharing the same WL. A preset erase voltage (V_(ERS)) is applied to all DLs and SLs, and Vpass is applied to WLs adjacent to the target WL, WL1-3 and WL1-1, to generate and inject holes by GIDL. 0V is applied to the target WL to inject holes into the charge storage layer. At this time, Vpass is applied to the WLs of the other layer to prevent hole injection. Here, V_(ERS) is a positive voltage large enough to generate holes by a gate induced drain leakage (GIDL) current between the WL line and the DL line and inject the holes into the insulator stack.

FIGS. 18A and 18B are graphs of read results for a synapse device (CELL A) that has performed a selective program operation and a synapse device (CELL B) that does not perform a selective program operation according to the selective program operation according to FIGS. 17A and 17B.

FIGS. 18A and 18B are results of measuring the current flowing in DL1 by applying a turn-on voltage to WL of the target cell after injecting holes into the target cell under the above-described condition of FIGS. 17A and 17B.

FIG. 18A is a graph of a read result for CELL A, which is a device subjected to an erase operation. The right line is the current in the initial state, and the left line is the current after the selective program operation. Referring to FIG. 18A, it can be seen that the current flowing through CELL A increases and changes from the initial state after the erase operation. Meanwhile, referring to FIG. 18B, it can be confirmed that the current flowing through CELL B after the selective erase operation on CELL A is the same as the initial state. That is, the HHI mechanism does not occur in CELL B adjacent to CELL A, so that the graph hardly changes.

In the above, the present invention has been described with respect to the preferred embodiment thereof, but this is only an example and does not limit the present invention. It will be appreciated that various modifications and applications not exemplified above are possible within the scope. And, the differences related to such modifications and applications should be construed as being included in the scope of the present invention defined in the appended claims. 

What is claimed is:
 1. A three-dimensional stackable synapse string, which comprises: a channel hole provided in the form of a pillar shape in a vertical direction, the inside of which is filled with an insulating material; a semiconductor body disposed on the surface of the channel hole and provided on the surface of the channel hole in the form of a thin layer; a plurality of first insulating layers disposed on an outer circumferential surface of the semiconductor body in a vertical direction; a plurality of word lines disposed on a first side surface of an outer circumferential surface of the semiconductor body and alternately provided with first insulating layers disposed on the first side surface; a plurality of insulator stacks positioned between the word lines and the semiconductor body; a device isolation unit positioned on an outer circumferential surface of the semiconductor body located on both sides of the first side surface, and including second insulating layers alternately stacked with the first insulating layers; a first electrode disposed on the channel hole and electrically connected to a first end of the semiconductor body; and a second electrode disposed under the channel hole and electrically connected to a second end of the semiconductor body; wherein the word line, the insulator stack, and the semiconductor body located on the first side of the semiconductor body constitute a synapse device or a part thereof, and the synapse devices stacked along the direction of the channel hole constitute a synapse string connected by the semiconductor body.
 2. The three-dimensional stackable synapse string according to claim 1, wherein the three-dimensional stackable synapse string is provided on a substrate having an upper surface formed of a first oxide layer, and the second electrode is provided on the surface of the first oxide layer.
 3. The three-dimensional stackable synapse string according to claim 1, wherein among the surface of the channel hole, the region where the synapse device is formed is protruded toward the word line and extended.
 4. The three-dimensional stackable synapse string according to claim 1, wherein the insulator stack is composed of a single insulating layer or a stack structure in which a plurality of layers are stacked; and when configured in a stack structure, the insulator stack comprises at least a charge storage layer and an insulating layer, at least a ferroelectric layer and an insulating layer, at least a resistance change layer and an insulating layer, or at least a phase change layer and an insulating layer.
 5. The three-dimensional stackable synapse string according to claim 1, which further comprises: a first electrode landing pad positioned on the first electrode, made of an electrically conductive material, and electrically connected to the first electrode; and a second electrode landing pad positioned on the first oxide layer located under the second electrode, made of an electrically conductive material, and electrically connected to the second electrode.
 6. The three-dimensional stackable synapse string according to claim 1, which further comprises an additional synapse string which includes: a plurality of additional word lines disposed on a second side surface of an outer circumferential surface of the semiconductor body opposite to the first side surface and alternately stacked with first insulating layers disposed on the second side surface; and a plurality of additional insulator stacks positioned between the additional second word lines and the semiconductor body; wherein the additional word line, the additional insulator stack and the semiconductor body located on the second side of the semiconductor body constitute an additional synapse device or a part thereof, and the additional synapse devices stacked along the vertical direction of the channel hole constitute an additional synapse string connected by a semiconductor body, respectively.
 7. The three-dimensional stackable synapse string according to claim 6, wherein the synapse string and the additional synapse string share the first electrode and the second electrode.
 8. The three-dimensional stackable synapse string according to claim 6, wherein the synapse string and the additional synapse string share a first electrode and include a second electrode separately.
 9. A three-dimensional stackable synapse array, characterized in that the three-dimensional synapse device strings according to claim 1 are arranged in an array form.
 10. The three-dimensional stackable synapse array according to claim 9, which further comprises a CMOS integrated circuit used as a peripheral circuit under the substrate.
 11. A method of manufacturing a three-dimensional stackable synapse string comprising the following steps: (a) forming a first oxide layer on a substrate, forming a second electrode landing pad on the first oxide layer, and planarizing the surface of the resultant; (b) alternately forming first insulating layers and second insulating layers on the surface of the first oxide layer on which the second electrode landing pad is formed to form a stacked structure; (c) etching predetermined regions of the stacked structure by using a photolithography process to simultaneously form an etch hole and a trench for string isolation, forming a passivation material in the etched regions of the stacked structure, and planarizing the surface; (d) etching the passivation material filled in the etch hole, depositing a semiconductor material on the surface of the etch hole to form a semiconductor body, filling the inside of the etch hole in which the semiconductor body is formed with an oxide layer, and planarizing the surface; (e) forming a first electrode landing pad on an upper portion of the semiconductor body; and (f) selectively etching a passivation material of the trench for string isolation, selectively etching second insulating layers from the surface of the trench for string isolation to be recessed, forming insulator stacks on the surfaces of the recessed spaces; and forming a plurality of word lines separated by layers by depositing and etching a conductive material;
 12. The method of manufacturing a three-dimensional stackable synapse string according to claim 11, wherein in the step (d), the passivation material filled in the etching hole is selectively etched, and the second insulating layers of the stacked structure are selectively etched and recessed to form a channel hole; and the semiconductor body made of a semiconductor material to be used as a channel is formed on the surface of the channel hole, and the inside of the channel hole is filled with an oxide material and then the surface of the resultant is planarized.
 13. The method of manufacturing a three-dimensional stackable synapse string according to claim 11, wherein the first insulating layer and the second insulating layer are made of materials having different etch ratios. 